1. Field of the Invention
The present invention relates generally to a bit line driver for a static read only memory of a microcomputer and more specifically to a bit line driver connected between a pair of complementary bit lines and having equalizing MOS transistors.
2. Description of the Prior Art
Conventionally, MOS memory units with a number of memory cells composed of MOS transistors arranged so as to write or read information in accordance with any given and selected addresses have widely been used as a storage device for an electronic computer. In order to shorten the access time of the MOS memory, it is necessary to increase the load resistance. However, as usual, since two MOS transistors are connected as active loads so as to function as a clamper, in order to obtain good clamping characteristics, it is necessary to sufficiently decrease the inner resistance of the two MOS transistors. In other words, two contradictory conditions have been required for a prior-art bit line driver in a MOS memory unit. Further, there exists another problem in that a high output clock amplifier is required to effect a precharge operation and equalization operations simultaneously. Furthermore, there exist the other drawbacks such that the stray capacitance of the bit lines is relatively great, causing a long discharge time and thereby preventing high speed operation.
The arrangement and operation of the prior art bit line driver for a MOS memory unit will be described in further detail with reference to the attached drawings in the detailed description of the preferred embodiment.